Hiring: Verification CAD Engineer Company: Sandisk Location: Milpitas, CA Job Posted Time: 2026-09-14 19:50:15 Target Skills & Keywords : Chai, HBase, Make, Python, SOC About the job Experience: •7+ years of Design Verif Required Skills: •We are seeking a self-directed Verification Methodology Engineer to design, build, and optimize the infrastructure that enables our global ASIC team to execute at high velocity. In this role, you will evaluate, integrate, and deploy advanced third-party verification tools and infrastructure solutions while defining robust methodologies across the entire development lifecycle. Beyond architectural ownership, you will serve as a critical technical resource for the broader ASIC team, proactively identifying and resolving workflow bottlenecks, debug challenges, compute resource constraints, and license limitations. •Role Overview •You will contribute to Sandisk verification architecture and the verification productivity suite by scaling new verification solutions into the global team using agents, skills and other advanced techniques. You will be responsible for the creative engineering required to make the global team more productive. Rather than executing a predefined script, you will identify inefficiencies then architect a framework to support solutions. Your goal is to build a portable, scalable environment where tools and infrastructure handle the complexity. •Essential Duties & Responsibilities •Methodology Innovation:Deploy scalable & portable methodologies that function across different environments scaling from IP to SOC to enable "write once, run anywhere" capability. •Cross-Functional Support:Provide expert-level support for ASIC Design and Verification teams. Provide the automation and workflows necessary for high-speed debug and data analysis. •Automation & Tooling:Build robust Python-based frameworks for automated testbench generation, regression management, and intelligent failure triage. •Infrastructure Architecting:Design, develop, and maintain CAD infrastructure for verification. Enable seamless handoffs between IP & SOC verification teams. Use advanced techniques like formal verification paired with AI to shift left verification development. Qualifications: •Education:B.S./M.S. in Electrical Engineering, Computer Engineering, or Computer Science. •ASIC DNA:7+ years of Design Verif Compensation: •$159,763 •$264,650 Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!