Hiring: Top Level Physical Design Engineer Company: Tenstorrent Location: Santa Clara, CA Job Posted Time: 2026-09-16 12:54:08 Employment Type: Hybrid Target Skills & Keywords : Microsoft Excel, SOC About the job Experience: •8+ years of top-level SOC physical design experience on complex, multi-million gate designs. Required Skills: •8+ years of top-level SOC physical design experience on complex, multi-million gate designs. •Deep expertise in hierarchical floorplanning, fabric implementation, power grid design, and global clock distribution. •Proven track record with bump planning, RDL implementation, and multi-voltage domain designs. •Mastery of timing closure, EM/IR analysis, and physical verification at the chip level. •How to implement cutting-edge AI accelerators and high-performance CPUs at the SOC level. •Advanced techniques for chiplet integration and next-generation packaging co-design. •Strategies for optimizing massive designs with complex power domains and clock architectures. •Methods for driving successful chip-level closure through effective cross-functional collaboration. Qualifications: •A seasoned physical design engineer who thrives on complex, full-chip implementation challenges. •Expert at collaborating across disciplines, working effectively with architecture, RTL, and packaging teams. •Passionate about optimizing chip-level implementations for power, performance, and area. •Detail-oriented professional who drives design closure while maintaining quality and meeting aggressive schedules. Compensation: •$100,000 - $500,000 / year Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!