System Performance Modeling Engineer
Qualcomm - San Diego, CA
Hiring: System Performance Modeling Engineer Company: Qualcomm Location: San Diego, CA Job Posted Time: 2026-09-10 13:59:36 Target Skills & Keywords : ASIC, C++, Machine Learning, Python, React, SOC About the job Experience: •5 years of solid experience in SoC modeling and/or software development; new graduates will be considered with strong internships & motivation. •2+ years of ASIC design, verification, validation, integration, or related work experience. •1+ year of ASIC design, verification, validation, integration, or related work experience. Required Skills: •Participate in NoC topology and system memory architecture exploration campaigns, working closely with key architects from various teams. Analyze complex datasets to identify insights and patterns that will help define the requirements for next-generation SoCs. •Drive architecture-oriented performance and power explorations across platform-level components (NoC, memory subsystem, system cache, memory controllers). •Develop new tools for architecture validation and exploration — focused primarily on performance and power modeling, with additional support for high-level functional validation. •Support exploratory methodology projects, involving machine learning, data science, etc. •Expand, maintain, and document innovative modeling frameworks. Participate in defining a new hardware modeling semantic, breaking with conventional hardware programming languages. •Robust understanding of computer architecture, memory hierarchy, and system/platform architecture. •Strong knowledge of Object-Oriented Programming (C++, Python). •Knowledge of bus components and interconnect micro-architecture. Qualifications: •Degree in Microelectronics, Computer Science, or related field. •Preferably 2–5 years of solid experience in SoC modeling and/or software development; new graduates will be considered with strong internships & motivation. •Understanding of interconnect protocols like AHB/AXI/ACE/ACE-Lite and NoC concepts and topologies. •Master's or PhD degree in Microelectronics, Computer Science, or related field. •Knowledge of NoC architecture and network traffic engineering. •Knowledge of Memory Controller, LPDDR & DDR protocols. •Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. •OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. •2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. OR PhD in Science, Engineering, or related field. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!