Hiring: Sr. Physical Design Engineer Company: Lumilens Location: San Jose, CA Job Posted Time: 2026-09-14 03:05:31 Target Skills & Keywords : ASIC, Make, Node.js, Perl, Python, Rocket About the job Experience: •8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below. Required Skills: •Senior Physical Design Engineer •Physical Implementation: Own full-chip and block-level physical implementation, including floorplanning, placement, CTS, routing, and physical verification for high-speed designs in advanced TSMC nodes. •Timing, Power, and Area Closure: Collaborate closely with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power closure across complex design blocks and full chip. •Advanced Physical Design: Apply physical design techniques for multi-voltage and multi-frequency domains, hierarchical implementation, physical-aware synthesis, congestion mitigation, skew optimization, and RC extraction-aware placement and routing. •Signoff and Tape out: Perform tapeout signoff activities, including PV, EM/IR, ESD and ejobview using industry-standard verification tools. Qualifications: •Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, or a related field. •Experience: 8+ years of hands-on physical design experience, preferably with advanced technology nodes at 5nm or below. •Physical Design Expertise: Strong experience with floorplanning, placement, CTS, routing, IR drop mitigation, timing closure, and signoff debugging. •Tools and Automation: Hands-on experience with tools such as Synopsys ICC2, RedHawk SC, Cadence Innovus, Voltus, Simens Calibre etc, along with strong scripting skills in Tcl, Python, or Perl. •High-Speed PHY Implementation: Experience with high-speed PHY such as SerDes, UCIe etc physical design implementation. •Advanced-Node Signoff: Familiarity with EM/IR analysis, power grid optimization, congestion analysis, physical verification, and tapeout signoff in advanced semiconductor process nodes. •High-Frequency Design Exposure: Experience supporting high-frequency datapath or DSP-heavy designs is a plus. •5D or 3D design experience: Experience with TSMC CoWoS or SoIC-X design experience is a strong plus. Compensation: •Competitive benefits and rewards package •Comprehensive benefits package including health insurance Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!