Hiring: SoC Physical Design Engineer Company: Nokia Location: San Jose, CA Job Posted Time: 2026-09-10 12:29:58 Employment Type: Hybrid Target Skills & Keywords : ASIC, EDA, Perl, Python About the job Experience: •3+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes •Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design •Scripting experience in TCL, python or Perl Required Skills: •Work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow, doing implementation to achieve best in class ASICs, which are optimized for power, performance and area metrics. •How You Will Contribute And What You Will Learn •Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip •Interface directly with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure •Perform technical evaluations of IP vendors, process nodes and provide recommendations •Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII •Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off •Perform Physical verification and IR/EM analysis on blocks as well as top Qualifications: •Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!