Hiring: SOC Architect, Reality Labs Silicon Company: Meta Location: San Diego, CA Job Posted Time: 2026-09-09 17:58:21 Employment Type: Full-time Target Skills & Keywords: SoC Architecture, Microarchitecture, Heterogeneous SoCs, CPU/GPU/NPU, ML Accelerators, Memory Hierarchy, Cache Hierarchy, DRAM Interface, NoC, High-Speed I/O (PCIe, USB, LPDDR), Hardware-Software Co-Design, Power Delivery, AR/VR/Wearable Silicon, Advanced Process Nodes, System MMU, Hardware Security Experience: - 8+ years of experience in SoC architecture, microarchitecture definition, or system-level hardware design for consumer electronics or mobile/wearable platforms - Experience architecting heterogeneous SoCs, encompassing CPU, GPU, neural processing, and hardware accelerator subsystems - Experience collaborating across hardware, firmware, and software disciplines to drive hardware-software co-design for real-time or latency-constrained workloads Required Skills: - Define and drive SoC-level architecture for AR or AI wearable chips, including compute subsystems, memory hierarchy, interconnect topology, and power delivery strategies - Lead architectural exploration and trade-off analysis across heterogeneous compute blocks, including CPU, GPU, vision, audio, and ML accelerators - Collaborate with algorithms, firmware, and software teams to drive hardware-software co-design decisions - Partner with IP vendors, power and performance architects, IP architects, and internal design teams to evaluate and integrate third-party and custom IP blocks into the SoC architecture - Develop architectural specifications, interface definitions, and design guidelines that guide RTL implementation and physical design teams - Provide architectural leadership and technical direction to other engineers across silicon, systems, and platform teams working on wearable device programs - Contribute to long-term silicon roadmap planning by evaluating emerging process technologies, memory technologies, and compute paradigms relevant to AR/VR applications - Expertise with high-speed I/O interfaces such as PCIe, USB, and LPDDR - Experience with memory subsystem architecture, including cache hierarchy design, DRAM interface optimization, and on-chip interconnect (NoC) design Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience - Preferred: Experience architecting silicon for AR, VR, or wearable devices with stringent power and thermal constraints - Preferred: Experience with AI/ML accelerator architecture and optimizing memory hierarchy for neural network workloads for on-device inference - Preferred: Familiarity with advanced process node design considerations (e.g., 5nm and below) and their implications for SoC architecture decisions - Preferred: Experience with system MMUs and hardware security Compensation: - Base pay range: $178,000.00/yr - $250,000.00/yr - Actual pay will be based on skills and experience Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don’t miss this opportunity to join a forward-thinking team!