Hiring: Senior Engineer, Physical Design (ASIC/SoC Place & Route) (Austin, TX)(5560) Company: TSMC Location: Austin, TX Job Posted Time: 2026-09-17 09:26:06 Employment Type: Hybrid Target Skills & Keywords : EDA, Foundry, Perl, R About the job Experience: •7+ years of industry experience. Required Skills: •Complete entire physical implementation of the block level and tapeout production chip •Block level floorplan with the ability to analyze the quality of the floorplan •Customized Clock tree structure and Place & Route •Implement ECOs for timing closure •Signal EM/Noise and Power IR/EM analysis and fix •DRC/LVS/ERC/ANTENNA analysis and clean up •The world’s leading dedicated semiconductor foundry •The technology leader with a strong reputation for manufacturing excellence Qualifications: •Master’s degree in Electrical/Computer Science Engineering with 7+ years of industry experience. •Netlist (or RTL)-GDS physical implementation experience •In depth knowledge of major EDA tools/design flows •Demonstrated capacity to work regularly at a Customer site in the North Austin, TX area •TSMC N5 and below technology •Able to independently complete Netlist-GDS P&R, signoff task •Proven record in multi-million gate design production tapeouts Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!