Hiring: Senior Digital Design Verification Engineer Company: Renesas Electronics Location: Austin, TX Job Posted Time: 2026-09-16 10:55:47 Target Skills & Keywords : Agile, Bash, Embedded Systems, Firmware, Linux, Perl, Python, SOC, SystemVerilog About the job Required Skills: •Independently own verification of significant blocks and features from planning through closure. The role combines hands-on UVM development, coverage-driven verification, complex debug, and close collaboration with architecture, RTL design, firmware, analog, validation, and systems teams. •Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure. •Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks. •Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models. •Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions. •Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data. •Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes. •Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools. Qualifications: •Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field. •4 or more years of relevant digital design verification experience, or equivalent directly applicable experience. •Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure. •Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions. •Hands-on experience developing and debugging reusable UVM environments and analyzing complex regression failures. •Strong RTL and testbench debug skills, with the ability to distinguish design, environment, test, firmware, and specification issues. •Solid functional working knowledge of digital design fundamentals, including state machines, clocks and resets, interrupts, register interfaces, memories, and clock-domain crossings. •Proficiency in Linux and at least one scripting language such as Python, Bash, Perl, or Tcl. •Demonstrated capacity to work independently and collaborate effectively across architecture, design, firmware, analog, validation, and systems teams. •Operational familiarity with PMBus, AVSBus, SVID or SVI3, I2C, SPI, or similar control and communication protocols. Compensation: •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!