Hiring: Senior Digital ASIC Design Engineer Company: Brookhaven National Laboratory Location: Upton, NY Job Posted Time: 2026-09-10 10:27:29 Employment Type: On-site Target Skills & Keywords : ASIC, CAD, EDA, FPGA, Firmware, Perl, Python, R, Shell, SystemVerilog, Verilog About the job Required Skills: •Take a lead role in the architecture, microarchitecture, RTL design, and integration of digital ASICs and digital subsystems for scientific instruments, including EIC detector readout and related programs •Develop design specifications based on detector, data acquisition, timing, power, radiation, and system integration requirements in conjunction with scientists, engineers, and project stakeholders •Design and implement synthesizable RTL in SystemVerilog/Verilog for blocks such as data formatting, sparsification, buffering, trigger and timing interfaces, configuration and control, calibration logic, digital signal processing, and high-speed link interfaces •Develop and maintain reusable digital IP, register maps, bus interfaces, clock and reset architectures, memory interfaces, finite-state machines, FIFOs, error detection/correction logic, and monitoring features suitable for ASIC integration •Carry out or contribute to synthesis, static timing analysis, clock-domain crossing analysis, reset-domain crossing analysis, power estimation, linting, design-for-test insertion, and timing-driven physical implementation in Cadence, Synopsys, Siemens, or similar CAD/EDA environments •Work closely with physical design and analog/mixed-signal teams to ensure successful floorplanning, partitioning, timing closure, power integrity, signal integrity, and mixed-signal integration •Coordinate with verification engineers to define verification plans, develop self-checking test benches, review functional coverage, debug simulations, and close design issues before tapeout •Support FPGA prototyping, laboratory evaluation, test-board development, bring-up, characterization, and integration of ASICs with sensors, firmware, and data acquisition systems Qualifications: •Bachelor's degree in electrical engineering, computer engineering, applied physics, or a closely related field of study •Minimum seven (7) years of progressively responsible related work experience in digital ASIC design •Demonstrated experience developing synthesizable RTL in SystemVerilog and/or Verilog for complex ASICs or system-on-chip designs •Operational familiarity with ASIC design processes and flows, CAD/EDA tools for ASIC design, and their interoperability across design, verification, synthesis, timing, and physical implementation •Demonstrated capacity to work effectively with group members in a multi-user, process-design-kit-managed, version-controlled design environment and to step up to technical and schedule challenges •Excellent written and oral communication skills, including the ability to document designs, participate in reviews, and work with multidisciplinary scientific and engineering teams •Master's or Ph.D. in electrical engineering, computer engineering, applied physics, or a closely related field of study •Operational familiarity with common on-chip bus and control interfaces such as AXI, AHB, APB, Wishbone, I2C, SPI, JTAG, and custom detector-readout protocols •Knowledge of radiation-tolerant design techniques, single-event-effect mitigation, triple modular redundancy, error detection/correction, and design approaches for low-power or cryogenic operation Compensation: •$115000 - $145000 / year Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!