Hiring: Senior Design Verification Engineer Company: Intel Location: Santa Clara, CA Job Posted Time: 2026-09-11 02:23:51 Employment Type: Internship / Hybrid Target Skills & Keywords : ASIC, C, C++, CAD, Chi, Compliance, EDA, FPGA, Foundry, Python, SOC, SystemVerilog About the job Experience: •Practical experience utilizing formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure •Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks •Shift 1 (United States of America) Required Skills: •Responsibilities Will Include But Are Not Limited To •Own verification planning and execution for key IP features across IP and subsystem integration points •Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models •Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality •Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics •Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams •Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows •Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality Qualifications: •Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field •10+ years of experience in design verification (DV); with extensive background in IP DV, and subsystem and SoC-level verification •Proven hands-on experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models •Proven hands-on experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature •Proven hands-on experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools •Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems •Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed. •Post graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!