Hiring: Senior Design Verification Engineer Company: Lumilens Location: San Jose, CA Job Posted Time: 2026-09-03 03:05:30 Target Skills & Keywords : ASIC, Compliance, FPGA, Firmware, Kind, Make, Move, Perl, Python, Rocket, SOC, Stimulus, SystemVerilog, Verilog About the job Experience: •3+ years of ASIC/SoC functional verification. Required Skills: •Build and extend UVM testbenches •(agents, sequences, scoreboards) for assigned blocks and subsystems. •Write directed and constrained-random tests •; develop functional coverage and drive it to closure. •Verify the in-house engines against an algorithmic golden model •, with programmable error injection and error-pattern coverage. •(e.g., UCIe) and run compliance, link-training, loopback, and lane-repair scenarios. •, and help maintain the CI/regression flow. Qualifications: •High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification •UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience •(Verilog-AMS or SV real-number models). •Emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium). •Exposure to NICs, Ethernet/IB switches, or cache-coherent fabrics •For control/interlock logic; portable stimulus. Compensation: •Competitive benefits and rewards package •Comprehensive benefits package including health, dental, and vision Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!