Hiring: Senior Design Verification Engineer - Neuromorphic Computing Company: Intel Location: Hillsboro, OR Job Posted Time: 2026-09-03 02:23:52 Employment Type: Hybrid Target Skills & Keywords : ASIC, Compliance, Event-Driven, Phoenix, Python, SOC About the job Experience: •3+ years of pre-silicon verification or post-silicon validation experience in SoC accelerators or custom ASIC designs. •3+ years of experience in UVM and constrained random verification methods. •2+ years of experience developing the entire verification stack from test planning to execution, e.g. covering test development, coverage tracking, emulation, and post-silicon. •1+ year of experience using AI tools for test generation, debugging and improving overall productivity. Required Skills: •Now, we're entering an exciting new chapter: transforming these breakthroughs into real-world products that will power the coming era of physical AI systems-beyond the reach of GPUs and mainstream AI accelerators. •If you are passionate about pushing the boundaries of computing, from transistor-level innovation to software abstractions, join us. Help define the next wave of AI technology that harnesses the proven advantages of Intel's neuromorphic computing technology with the versatility demanded by modern AI workloads. •An openness to learning new technologies and methodologies, such as asynchronous design techniques and AI-driven verification automation, is essential. •Mapping application-level requirements to unit- and system-level test plans. •Write Python-based directed and random tests for design partitions and chip-level. •Running regressions, debugging test failures, tracking coverage and working with designers to fix failures and improve coverage. •Maintaining assertions, scoreboards and any tools/flows that are developed. •Integrating VIPs and coordinating with IP teams to ensure protocol requirements are met. Qualifications: •Bachelors and 5+ years OR Masters and 3+ years of silicon engineering experience. •3+ years of pre-silicon verification or post-silicon validation experience in SoC accelerators or custom ASIC designs. •3+ years of experience in UVM and constrained random verification methods. •2+ years of experience developing the entire verification stack from test planning to execution, e.g. covering test development, coverage tracking, emulation, and post-silicon. •1+ year of experience using AI tools for test generation, debugging and improving overall productivity. •Experienced in neuromorphic computing or AI/ML accelerator design. •Practical experience utilizing commercial Verification IPs for standard IO interfaces, PHYs, and protocols such as Ethernet, PCIE, MACsec/IPsec, RoCEv2, MIPI CSI-2, JESD204. •Practical experience utilizing DFX, low power and UPF verification techniques. •Shift 1 (United States of America) •US, Arizona, Phoenix, US, California, Folsom, US, California, Santa Clara, US, Texas, Austin Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!