Hiring: Senior Density Fill Development Engineer Company: Intel Location: Hillsboro, OR Job Posted Time: 2026-09-10 02:23:52 Employment Type: Hybrid Target Skills & Keywords : Compliance, EDA, Foundry, Linux, Make, Phoenix About the job Experience: •5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment. •3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications. •5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization. •Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment. Required Skills: •Design, develop, and debug Fill components of Process Design Kits (PDKs), •Provide algorithmic solutions using tools such as Calibre, ICV, and Pegasus to address density deficiencies and ensure manufacturability compliance. •Partner cross-functionally with process developers, design rule owners, and end users to define requirements and implement state-of-the-art solutions. •Automate workflows to enhance efficiency, accuracy, and deployment across design teams. •Develop comprehensive test cases and systems to validate software tools and ensure seamless integration with various design methodologies. •Innovate and drive advancements in EDA tools and methodologies to meet the evolving needs of Intel's technology ecosystem. •Partner with cross-functional teams and external EDA vendors to define and implement new tool features and methodologies. •Maintain documentation, including training materials and user guides, to support customers and ensure robust deployment. Qualifications: •Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 8+ years of experience, Master's degree with 5+ years of experience, or PhD with 2+ years of experience. •Minimum 5 years of hands-on experience with at least one industry-standard physical verification platform (Calibre, ICV, or Pegasus), including methodology development, rule deck debugging, or production deployment. •3+ years of direct experience developing, maintaining, or debugging physical verification rule decks using SVRF, TVF, PXL, or PVL/PVTCL for DRC, density, or fill verification applications. •Solid understanding of semiconductor device physics, process technology, and design rules. •Proven hands-on experience in developing algorithmic solutions for physical design challenges in advanced manufacturing nodes. •Strong knowledge of Unix/Linux platforms and computing environments. •5+ years of hands-on experience developing, deploying, or supporting density fill methodologies for semiconductor technologies at 16nm and below, including ownership of fill rule implementation, density compliance, or manufacturability optimization. •Practical experience utilizing advanced physical verification techniques, including DRC, and density/fill modules. •Industry experience with other foundry technologies in this domain is strongly desirable •Operational familiarity with custom layout tools such as Cadence Virtuoso or Synopsys Custom Designer. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!