Hiring: RFIC Silicon Lead Company: Tacit Location: San Francisco, CA Job Posted Time: 2026-09-11 10:44:36 Target Skills & Keywords : Agile, Node.js, SOC About the job Experience: •10+ years in RFIC design, with substantial industry experience delivering silicon Required Skills: •The rare skill we are looking for is not generic RFIC execution. It is the ability to reason across system architecture, low-power CMOS RF, frequency generation, sensing constraints, form factor, and product requirements — and to know when a proposed path will or will not work in silicon. •Help decide what stays internal and what is executed with external silicon partners. You may directly own blocks, technically direct contractors, or build the internal team. In all cases, the architecture-defining IP and technical judgment must live inside Tacit. •Define the RF CMOS architecture for an ultra-low-power, frequency-agile sensing front end •Translate system-level sensing, ML, and form-factor constraints into circuit-level requirements •Design and/or technically direct critical RF circuit blocks, including VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, biasing, and power-management structures •Architect fast-settling frequency generation and hopping approaches suitable for aggressive duty-cycled operation •Drive power-reduction methodology across the RF system: duty-cycle co-design, supply gating, bias trimming, wake/sleep transients, and system-level power tradeoffs •Evaluate and recommend CMOS process options for a low-power wideband / frequency-agile SoC, including tradeoffs across 28nm, 22FDX, 55nm RF, and related nodes Qualifications: •MS or PhD in electrical engineering, or equivalent experience •Deep experience in low-power CMOS RF, synthesizers, radar, UWB, frequency-agile radios, or related sensing systems •Strong transistor-level design ability in Cadence Virtuoso, Spectre, and ADE •Expertise in synthesizer and RF front-end circuits, especially VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, and biasing •In-depth knowledge of CMOS process tradeoffs, device behavior, stack selection, parasitics, layout effects, and RF process-node selection •Track record taking RFIC blocks or systems from architecture through silicon validation •Demonstrated capacity to reason across architecture, circuits, layout, packaging, measurement, power, and product constraints •Demonstrated capacity to translate ambiguous system-level goals into concrete circuit and silicon tradeoffs •Strong communication skills and ability to lead technical decisions in a small, fast-moving team •Background in low-power radar, UWB, frequency synthesizers, or frequency-agile sensing front ends Compensation: •$180,000 - $230,000 / year •$180,000 - $230,000/year plus meaningful equity package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!