Hiring: R&D Engineer IC Design Company: Broadcom Location: San Jose, CA Job Posted Time: 2026-09-17 01:07:09 Target Skills & Keywords : SystemVerilog, Verilog About the job Experience: •6 years of work experience in Design Verification Required Skills: •The annual base salary range for this position is $120,000 - $192,000 •This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements. Qualifications: •A Master's Degree in Electrical and Electronic Engineering, Computer Science, or equivalent •A minimum of 6 years of work experience in Design Verification •Strong knowledge and hands-on experience in verification methods, tools and environment •Strong programming skills, including in System Verilog and scripts languages •Knowledge and experience in UVM methodology is preferable •Knowledge of networking and switching concept is a plus Compensation: •$120,000 - $192,000 / year •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!