Hiring: R&D Engineer IC Design 4 Company: Broadcom Location: Austin, Texas Metropolitan Area Job Posted Time: 2026-09-11 13:07:09 Target Skills & Keywords : ASIC, Git, Perl, SVN, Verilog About the job Experience: •Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience •8+ years of related experience; or Masters degree and 6+ years of related experience Required Skills: •Demonstrated capacity to work independently as well as part of a large team spanning multiple geographies. •Synthesis experience with either Synopsys Design Compiler/ DC topo or Cadence RTL compiler •Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries •Understanding of liberty LIB models for timing •Formal verification (Synopsys Formality / Cadence Conformal) •Power analysis of RTL and gate level netlists •Operational familiarity with DFT (design for test) and scan methodology •Version control Compensation: •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!