Hiring: R-10066168 Physical Design Methodology Lead Company: NXP Semiconductors Location: Austin, TX Job Posted Time: 2026-09-10 13:35:47 Target Skills & Keywords : ASIC, AutoCAD, CAD, Data Pipeline, EDA, Embedded Systems, Foundry, Machine Learning, Node.js, Perl, Python, SOC, Shell About the job Experience: •10+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products. Required Skills: •Own, develop, and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, with emphasis on quality of results, scalability, runtime, and designer productivity. •Drive methodology development across place and route, CTS, timing closure, congestion analysis, ECO implementation, power grid design, IR/EM analysis, extraction, and signoff readiness. •Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to ensure flows meet tapeout requirements for complex SoC and IP programs. •Lead initiatives from concept and feasibility assessment through prototype development, benchmarking, validation, documentation, deployment, training, and production support. •Establish repeatable best practices, reference flows, automation frameworks, dashboards, and metrics to improve PPA, reduce turnaround time, and improve predictability across projects. •Work closely with EDA vendors to evaluate, enable, and adopt the latest technologies in physical implementation, signoff, power integrity, machine learning optimization, and agentic/AI-assisted design automation. •Conduct competitive benchmarking and technology evaluations to identify flow gaps, quantify benefits, and influence vendor roadmaps. •Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues, and provide expert guidance to design implementation teams. Qualifications: •Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. •Typically, 10+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products. •Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification. •Comprehensive expertise in timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, setup/hold optimization, and correlation across implementation and signoff tools. •Proven ability to improve PPA through methodology innovation, tool tuning, automation, and cross-functional problem solving. •Strong scripting and automation skills using Tcl, Python, Perl, shell scripting, or equivalent technologies. •Demonstrated ability to influence technical direction, communicate complex topics clearly, and drive cross-team initiatives to closure. •Operational familiarity with AI/ML-driven EDA optimization, design-space exploration, predictive analytics, automated debugging, and agentic workflow concepts. •Strong vendor engagement experience, including tool evaluation, benchmark definition, issue escalation, roadmap influence, and early technology adoption. •Demonstrated capacity to mentor engineers, define technical standards, and act as a trusted methodology expert across multiple design teams. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!