Hiring: Physical Design Engineer - STA Company: Oho Group Location: Austin, Texas Metropolitan Area Job Posted Time: 2026-09-03 10:22:20 Target Skills & Keywords : ASIC, CAD, EDA, Python, SOC, Shell About the job Experience: •5+ years of industry experience, or Ph.D. with 3+ years. Required Skills: •Develop STA flows and methodology using Cadence Tempus or Synopsys PrimeTime for advanced FinFET technologies. •Own timing convergence for IP, subsystem, and SoC blocks. •Define timing corners, margins, extraction methodology, and signoff correlation. •Develop slew, glitch/noise, and custom timing checks. •Define and drive SDC constraints with RTL, DFT, and IP teams. Qualifications: •M.S. in Electrical Engineering with 5+ years of industry experience, or Ph.D. with 3+ years. •Multiple STA signoffs/tape-outs at 12nm or below. •Strong experience with Cadence, Synopsys, or Mentor EDA tools. •Applied hands-on capability in high-frequency, low-power timing convergence. •Deep knowledge of STA, constraints, exceptions, corners, voltage definitions, and timing margins. •Strong TCL, shell, and Python scripting skills. •Understanding of low-power implementation and power/timing tradeoffs. •Knowledge of computer architecture, physical design, ASIC implementation, and full-chip signoff. •This role can be in San Francisco or Austin •We are not able to sponsor Visas Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!