Hiring: Physical Design Engineer, PnR Company: Tenstorrent Location: Santa Clara, CA Job Posted Time: 2026-09-13 12:54:08 Employment Type: Hybrid Target Skills & Keywords : SOC About the job Required Skills: •Execute synthesis, PNR, and STA for assigned partitions of a complex AI SoC. •Help close EM/IR, ensure UPF power intent is consistent with implementation, and drive LEC and physical verification signoff for your partitions in coordination with methodology owners. •Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks. •How to implement and close AI SoC partitions end-to-end, including power intent, timing, and physical signoff in a modern Synopsys-based flow. •Deeper expertise across signoff domains: EM/IR, DRC/LVS, logical equivalence (LEC/Formality), and CDC-aware implementation on meaningful production blocks. •Practical integration of analog/mixed-signal macros (PLL/DLL), DFT features (OCC/MBIST), and SoC interface IP within advanced physical design flows and collaborative tapeout environments. Qualifications: •Comfortable in a small, cross-functional physical design team, owning a block or subsystem and partnering on tapeout milestones with clear communication and accountability. •Ideally bring extra depth in areas such as UPF/multi-voltage power domains, SoC interface IP integration (e.g. I3C, UART), signoff breadth (DRC/LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical implementation (OCC/MBIST). Compensation: •$100,000 - $500,000 / year Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!