Hiring: Microarchitect / RTL Design - Network Datapath & MAC Engine Company: Architect Labs Location: Palo Alto, CA Job Posted Time: 2026-09-12 11:33:35 Target Skills & Keywords : FPGA, Node.js, Python, SOC, SystemVerilog About the job Experience: •: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving networking or packet-processing silicon (NICs, switches, SmartNICs, or networking SoC subsystems). •: Deep familiarity with IEEE 802.3 Ethernet standards — MAC sublayer operation, PCS encoding (64b/66b, Reed-Solomon FEC), reconciliation sublayer, and multi-lane distribution/alignment. •MAC Engine Design •: Hands-on experience designing or owning Ethernet MAC blocks including Tx/Rx pipelines, inter-packet gap management, preamble/SFD processing, FCS computation, VLAN tagging, and jumbo frame support. •: Clear, synthesizable, lint-clean RTL with strong design habits — parameterization for multi-rate support, modularity for protocol layering, and configurability for different deployment targets. Required Skills: •Own the network datapath RTL end-to-end •: from IEEE 802.3-compliant MAC engine design through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow. •Design and implement Ethernet MAC engines •: including 802.3 MAC/PCS layers, FCS generation/checking, flow control (802.3x pause, PFC), auto-negotiation state machines, and rate adaptation logic for multi-speed operation (10G/25G/50G/100G/400G+). •: including Tx/Rx FIFO management, packet buffering and scheduling, credit-based flow control, descriptor management, and DMA interfaces for host-to-network data movement. •Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs (latency vs. throughput vs. area), and feed area/timing/power realities back into the architecture and internal AI systems. •Define and maintain interface specifications •: MII/GMII/XGMII/CGMII variants, AXI-Stream for packet data, AXI for CSR/DMA, and custom sideband signaling for scheduling and QoS. Qualifications: •: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. •Operational familiarity with RDMA, RoCEv2, or TCP offload engine architectures. •Low-power design techniques: clock gating for idle ports, power gating for unused lanes, multi-voltage domains. •FPGA prototyping experience (Xilinx Vivado/Vitis), especially with Ethernet hard IPs or soft MAC cores. •SVA assertions for protocol compliance checking (e.g., inter-frame gap, pause quanta timing, alignment marker lock). •Prior IP building and delivery experience for Ethernet MAC/PCS or NIC subsystem blocks. •Domain-specific research contributions: publications or patents in network-on-chip, datacenter networking, or high-performance packet processing hardware. •You’ll join a founding team building the future of chip design at the intersection of AI and silicon. Your networking expertise will directly shape production ASICs and influence how AI transforms hardware development — from spec to tapeout. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!