Hiring: Microarchitect / RTL Design - Interconnect & Fabric Company: Architect Labs Location: Palo Alto, CA Job Posted Time: 2026-09-11 03:05:31 Target Skills & Keywords : Chi, Compliance, FPGA, Gatling, Node.js, Python, SOC, SystemVerilog About the job Experience: •: 5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience involving on-chip interconnects, NoC fabrics, or high-speed I/O subsystems. •: Deep familiarity with ARM AMBA protocol suite — AXI4/AXI5 (channel mechanics, burst types, ordering, exclusive access), ACE/ACE-Lite (coherence transactions, snoop channels), CHI (request/response/data/snoop flits, home nodes, snoop filters), and legacy AHB/APB for peripheral integration. •NoC/Fabric Design •: Hands-on experience designing or owning crossbar switches, NoC routers, or multi-layer interconnects including arbitration schemes (round-robin, priority, age-based, bandwidth-regulated), virtual channel management, flow control (credit-based, ready/valid), and QoS mechanisms. •: Experience with HSIO bridge logic — PCIe root complex/endpoint bridge design, CXL.io/CXL.mem/CXL.cache protocol translation, or custom chip-to-chip links (UCIe, proprietary die-to-die) including link-layer protocols, credit management, and replay/retry logic. Required Skills: •Own the on-chip fabric RTL end-to-end •: from NoC topology and router microarchitecture through code generation, lint, CDC, synthesis, and timing closure using our AI-driven design flow. •Design and implement AMBA-based interconnect fabrics •: including AXI/ACE/CHI-compliant crossbar switches, network interfaces (NIs), protocol converters (AXI-to-CHI bridges, AXI-to-AHB/APB downconverters), and multi-layer interconnect configurations optimized for ML accelerator traffic patterns. •Architect NoC routers and topologies •: including virtual-channel routers, wormhole/flit-based switching, adaptive routing algorithms, QoS-aware arbitration (bandwidth regulation, latency-critical path prioritization), and deadlock-free network design for mesh/ring/tree topologies. •Design high-speed I/O fabric bridges and peer-to-peer engines •: including PCIe/CXL-to-fabric bridges, chip-to-chip interconnect logic (UCIe, custom die-to-die links), peer-to-peer DMA controllers for direct device-to-device transfers bypassing host memory, and coherent/non-coherent multi-chip fabric extensions. Qualifications: •: Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or a closely related field. •Practical experience utilizing coherent multi-chip/multi-die interconnect architectures (chiplet-based designs, UCIe, BoW). •Operational familiarity with hardware coherence protocols: MOESI/MESIF state machines, snoop filter design, directory-based coherence. •Practical experience utilizing network-on-chip research: adaptive routing, congestion management, topology optimization, or formal deadlock analysis. •Low-power design techniques for interconnect: clock gating idle ports, power gating unused links, link-level power states (L0s/L1), dynamic frequency/width scaling. •FPGA prototyping experience (Xilinx Vivado/Vitis), especially with AXI interconnect IPs, NoC IPs (Versal), or custom fabric implementations. •SVA assertions for protocol compliance: AXI ordering rules, CHI transaction flows, deadlock detection, and livelock/starvation monitors. •Prior IP building and delivery experience for NoC IPs, AXI interconnect IPs, PCIe controllers, or CXL endpoint/switch IPs. •Performance modeling: experience building or using NoC simulators (e.g., BookSim, Garnet) or system-level traffic models to validate fabric microarchitecture. •Domain-specific research contributions: publications or patents in on-chip networks, interconnect architectures, or high-performance data movement for ML/HPC workloads. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!