Hiring: Member of Technical Staff - Microarchitect / RTL Design Company: Architect Labs Location: Palo Alto, CA Job Posted Time: 2026-09-10 11:57:48 Target Skills & Keywords : ASIC, FPGA, Node.js, Python, SOC, SystemVerilog About the job Experience: •5+ years (10+ preferred) in RTL design with at least one advanced-node tapeout experience, worked on specialized HW accelerators. •Clear, synthesizable, lint-clean RTL with strong design habits such as parameterization, modularity, reuse and configurability. •Applied hands-on capability in block-specific compute datapaths and data movement; such as MAC arrays, vector units, accumulators, on-chip SRAM controllers and arbiters, DMA engines, scratchpad memory management, etc. •Solid grasp of synthesis, timing constraints, clock domain crossings, reset strategies, AMBA protocols (AXI, AHB, APB), power management techniques, etc. •Strong skills for design automation, regression infrastructure, and tooling. Required Skills: •As a lab, we are investing in building a world-class HW design team, so if you think you have a particular experience/background that is not listed here, please still reach out to us! •Own AI-driven RTL design flow end-to-end (at the frontend): through code generation to incorporating feedback from lint, CDC, synthesis, and timing closure stages for closing the design loop. •Work directly with the principal architect to refine microarchitectural specs, resolve implementation trade-offs, and feed area/timing/power realities back into the architecture and internal AI systems. •Define and maintain interface specifications (e.g. AXI, AXI-Stream, or custom-built) for block- and SS-level integration. •Build and maintain RTL infrastructure for our in-house AI-driven flow: design automation scripts, regression flows, lint/CDC waivers, and integration collateral. •Close collaboration with DV: Support DV bring-up with reference models, assertions, test-plans, and architectural documentation for verification closure. •Close collaboration with SW and ML: Support and guide our SW and ML experts to revise and improve our in-house AI flow based on your own experience. •Support FPGA prototyping on Xilinx for early functional validation. Qualifications: •Low-power design techniques: clock gating, power gating, multi-voltage domains, UPF. •FPGA prototyping experience (ideally Xilinx Vivado/Vitis). •Operational familiarity with SIMD/VLIW execution pipelines or instruction-driven datapath design. •Prior IP building and delivery experience on your block-of-expertise, such as DMA controllers, memory subsystems, interconnects, or similar SoC infrastructure blocks. •Domain-specific expertise: Track record on research and development on energy-efficient, high-performance HW accelerators on your block-of-expertise. Compensation: •Competitive salary and meaningful equity stake Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!