Hiring: Lead ASIC Design Engineer Company: Broadcom Location: San Jose, CA Job Posted Time: 2026-09-16 13:07:09 Target Skills & Keywords : ASIC, EDA, Foundry, Perl, Python, SOC, SystemVerilog, Verilog About the job Experience: •12+ years of direct industry experience in ASIC/SoC digital design, with a proven track record of owning chip projects or serving as a design lead. Required Skills: •Technical Ownership: Serve as the central Chip Lead, defining top-level digital architecture, partitioning hard/soft IP blocks, and owning the complete integration lifecycle. •Cross-Discipline Alignment: Act as the bridge between Logic Design, Physical Design (PD), Architecture, and Design Verification (DV) to ensure all PPA (Power, Performance, Area) targets are met. •Tape-Out Delivery: Own and drive the final tape-out sign-off checklist, coordinating across all technical teams to ensure a clean handoff to the foundry. •Mentorship & Culture: Provide technical guidance, code reviews, and architectural mentorship to mid-level and junior engineers on the team. •RTL Design: Author, optimize, and maintain high-quality, synthesizable SystemVerilog/Verilog RTL for complex digital blocks, control logic, clocking structures, and register files (CSRs). •Timing & Constraint Ownership: Drive top-level chip timing constraints (SDC), define the Clock Domain Crossing (CDC) strategy, and establish block-level timing budgets for the PD team. •Front-End Flows: Drive logic synthesis (e.g., Design Compiler, Genus), Static Timing Analysis (STA via PrimeTime/Tempus), and run static quality checks (Lint, SpyGlass, JasperGold CDC). •IP Management: Manage the integration of custom internal analog macros, mixed-signal blocks, and third-party soft/hard IP. Qualifications: •RTL Mastery: Expert-level proficiency in SystemVerilog/Verilog digital logic design and microarchitecture principles. •Tool Fluency: Deep experience with front-end EDA tools for synthesis, STA, and CDC analysis (e.g., Synopsys or Cadence tool suites). •Silicon Track Record: Must have a proven history of successful, first-pass silicon tape-outs on modern process technologies. •Communication: Outstanding documentation and verbal communication skills; this role authors the authoritative architectural and design specifications for the entire project. •Work Authorization: Must have legal authorization to work in the US. Compensation: •$143,800 - $230,000 / year •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!