Hiring: Lead ASIC Design Engineer Company: Oho Group Location: San Jose, CA Job Posted Time: 2026-09-16 10:22:20 Target Skills & Keywords : ASIC, SOC, SystemVerilog, Verilog About the job Experience: •10+ years of ASIC/SoC design experience Required Skills: •RTL design and microarchitecture •Work on cache-coherent and non-coherent interconnects and associated protocols. •Define and review microarchitectural specifications and translate them into robust, synthesizable RTL. •Work closely with verification engineers on design validation, debugging and performance analysis. •Partner cross-functionally with architecture, verification, software and system teams throughout the silicon development cycle. •, with substantial hands-on RTL development. •Verilog/SystemVerilog RTL design experience. •SoCs, NoCs, interconnects, fabrics or high-performance processors Qualifications: •BS, MS or PhD in Electrical Engineering, Computer Engineering, Computer Science or a related field. Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!