Hiring: Lead Analog IC Designer Company: Cadence Location: San Jose, CA Job Posted Time: 2026-09-03 07:38:38 Target Skills & Keywords : CAD About the job Experience: •3 years of experience in CMOS SerDes or high-speed I/O IC design and development Required Skills: •Responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. •Candidate’s background should include a minimum of 3 years of experience in CMOS SerDes or high-speed I/O IC design and development •Solid functional working knowledge of a set of common SerDes standards and their electrical requirements is a plus •Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators •Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment •Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification •Cadence tool experience, lab test experience, and design experience at >112Gbps and in <7nm technologies are a plus •We’re doing work that matters. Help us solve what others can’t. Qualifications: •MS or PhD in EE Compensation: •$114,800 - $213,200 / year •You may also be eligible to receive incentive compensation: bonus, equity, and benefits Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!