Hiring: Hardware Technical Program Manager Company: Efficient Computer Location: Austin, TX Job Posted Time: 2026-09-16 23:16:23 Target Skills & Keywords : ASIC, Confluence, EDA, FPGA, Firmware, Foundry, Jira, Program Management, SOC About the job Experience: •5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution •10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution •7+ years in semiconductor/hardware engineering or program management, including at least 2 full SoC/ASIC programs taken from concept through tapeout and silicon bring-up. Required Skills: •Own the silicon schedule from architecture freeze through tapeout, bring-up, and production with the schedule informed by customer requirements and internal functional leads. •Strategically drive weekly execution cadence (program reviews, design reviews, tapeout readiness) and maintain a single source of truth for status, dependencies, and decisions. •Coordinate handoffs across architecture, RTL, DV/emulation, DFT, physical design, IP, package, and software •Manage the dependency chains hardware programs live and die on: IP delivery, PDK/library releases, EDA versions, and emulation capacity. •Run the tapeout checklist and signoff matrix (timing, power, IR/EM, DRC/LVS, DFT coverage, ECO closure, GDS handoff), holding owners to closure criteria. •Interface directly with supply chain/logistics for: IP acquisition, silicon arrival, ATE/loadboard readiness, lab scheduling, bug triage, and ECO/respin decision support. •Manage Risk & Decisions •Surface risk early with mitigation options and schedule impact quantified — late IP, coverage shortfalls, convergence misses, foundry slot changes. Qualifications: •B.S. in Electrical/Computer Engineering, Computer Science, or equivalent; M.S. or MBA a plus. •Working fluency in the chip design flow: RTL, functional verification and coverage closure, DFT, synthesis, PnR, STA, physical signoff (DRC/LVS/IR/EM), GDSII handoff, and post-silicon validation. •Demonstrated ability to build and defend a bottoms-up schedule with critical path analysis and dependency mapping. •Track record influencing without authority — earning the technical credibility to push senior engineers on commitments and dates. •Strong written and verbal communication; able to run a room of principal engineers and an exec review with equal effectiveness. •Hands-on with program tooling: Jira, Confluence, MS Project/Smartsheet, and familiarity with the Synopsys/Cadence/Siemens EDA ecosystem. •Prior hands-on engineering experience in design, DV, or physical design before moving to program management. •Operational familiarity with AI/ML accelerators, dataflow or novel compute architectures.. •Exposure to package/board co-design programs (FC-BGA, WLCSP) and OSAT coordination. •Operational familiarity with quality and compliance frameworks relevant to the target market (automotive, industrial, or security certifications). Compensation: •$200,000 - $240,000 / year •Flexible work environment (work from home / hybrid options) •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!