Hiring: Full-Chip Physical Design Verification Engineer Company: Tenstorrent Location: Santa Clara, CA Job Posted Time: 2026-09-10 12:54:08 Employment Type: Hybrid Target Skills & Keywords : AutoCAD, CAD, Foundry, Python, SOC About the job Experience: •14 years of hands-on CPU/IP/SoC physical verification experience. Required Skills: •BS/MS in Electrical/Electronics Engineering (or related) with 7–14 years of hands-on CPU/IP/SoC physical verification experience. •Proven expertise in DRC, LVS, ERC, PERC, Antenna, and DFM verification using industry-standard tools and flows. •Strong background in ESD planning, padring integration, bump/RDL strategies, and reliability analysis (IR drop, EM), with solid understanding of advanced nodes (7nm, 5nm, 3nm) and FinFET design challenges. •Scripting proficiency in Python and TCL for automation and flow optimization. •Advanced physical verification methodologies and flow optimization for next-generation SoCs. •Integration and verification strategies for full-chip signoff across advanced process technologies. •Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts. •Leadership and mentoring opportunities in building scalable PV methodologies and automation. Qualifications: •A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure. •A hands-on problem solver who excels at debugging and driving signoff through complex verification flows. •A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces. •A mentor and technical leader passionate about building efficient, manufacturable silicon. Compensation: •$100,000 - $500,000 / year Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!