Hiring: Formal Verification Engineer Company: LanceSoft, Inc. Location: Austin, TX Job Posted Time: 2026-09-10 10:57:46 Target Skills & Keywords : EDA, Embedded Systems, Perl, Python, SystemVerilog, Verilog About the job Required Skills: •Applied hands-on capability in VC Formal (Synopsys) and/or Jasper Gold (Cadence) •Strong proficiency in System Verilog Assertions (SVA) and formal property specification •Operational familiarity with scripting languages (TCL, Python, Perl) for flow automation •Extensive experience in design verification with a strong focus on formal verification •Expertise in System Verilog and UVM-based verification methodologies - Nice to have Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!