Hiring: Formal Verification - DV Company: Etched Location: San Jose, CA Job Posted Time: 2026-09-10 13:19:14 Employment Type: Contract Target Skills & Keywords : ASIC, Firmware, Perl, Python, SOC, SystemVerilog About the job Experience: •5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon. Required Skills: •Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic. •Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom. •Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models. •Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence. •Interface directly with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria. •Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up. •Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis. •Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices. Compensation: •Medical, dental, and vision packages with generous premium coverage Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!