Hiring: Design Verification Manager Company: BayOne Solutions Location: Sunnyvale, CA Job Posted Time: 2026-09-11 10:31:30 Employment Type: Hybrid Target Skills & Keywords : AI, ASIC, Interaction Design, Machine Learning, SOC, Stimulus, SystemVerilog About the job Experience: •10+ years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification. •5+ years of dedicated engineering management or formal team leadership experience directly managing engineering headcount, performance reviews, and project delivery schedules. Required Skills: •We are seeking a visionary and technically rigorous Design Verification Manager to lead our world-class silicon verification team. In this pivotal leadership role, you will architect, guide, and execute advanced verification strategies for high-performance, next-generation semiconductor products. •Team Leadership & Mentorship: Manage, inspire, and grow a team of high-performing design verification engineers. Foster a culture of technical excellence, continuous learning, and collaborative accountability. •Allocating resources effectively across multiple parallel chip/block schedules. •Verification Strategy & Architecture: Define global verification strategies, infrastructure, and execution plans for complex SoC and IP blocks. Own the testbench architecture from initial specifications down to structural sign-off. •Methodology Champion: Drive standard-setting execution using industry-best paradigms, ranging from advanced functional metric tracking to pioneering automated flows. Lead the team across block, sub-system, and full-chip verification environments. •Cross-Functional Collaboration: Align closely with Architecture, RTL Design, Physical Design, and Post-Silicon validation teams to identify coverage gaps, debug system-level failures, and ensure timely tape-out milestones. Qualifications: •Languages & Frameworks: Deep, expert-level fluency in SystemVerilog and Universal Verification •Formal Verification: Proven track record of leveraging formal methods to definitively mathematically prove block-level assertions and catch deep corner-case bugs. •Emulation & Hardware Acceleration: Strategic experience utilizing emulation platforms (e.g., Palladium, Zebu, Veloce) to shift-left software integration and accelerate massive system-level test suites. •Verification Experience: 10+ years of deep, hands-on industry experience in pre-silicon ASIC/SoC Design Verification. •Leadership Experience: 5+ years of dedicated engineering management or formal team leadership experience directly managing engineering headcount, performance reviews, and project delivery schedules. •Proven mastery building scalable UVM-compliant testbenches from scratch. •Advanced Education: Master's degree or Ph.D. in Electrical Engineering or Computer Science. •AI/ML in Verification: Exposure to, or hands-on experience implementing, Artificial Intelligence and Machine Learning techniques within verification pipelines (e.g., using AI/ML for smart stimulus generation, coverage convergence acceleration, automated bug triage, or regression optimization). •Demonstrated capability to manage globally distributed engineering teams. Compensation: •$170,000 - $200,000 / year Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!