Hiring: Design Verification Engineer - Interface IP Company: Etched Location: San Jose, CA Job Posted Time: 2026-09-10 13:19:14 Target Skills & Keywords : SOC, SystemVerilog, Verilog About the job Experience: •5+ years of design verification experience Required Skills: •End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors •Understand vendor IP configurations and handle handshake with internal IP team •Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications. •Partner cross-functionally with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture. •Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios. •You may be a good fit if you have •5+ years of design verification experience •You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs. Compensation: •$150,000 - $275,000 / year •Medical, dental, and vision packages with generous premium coverage Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!