Hiring: ASICS Design Verification Engineer-Senior Company: Qualcomm Location: San Diego, CA Job Posted Time: 2026-09-13 18:01:55 Target Skills & Keywords : C, C++, Perl, Python About the job Experience: •2+ years of ASIC design, verification, validation, integration, or related work experience. •1+ year of ASIC design, verification, validation, integration, or related work experience. •2+ years of experience with ASIC design and verification tools, techniques, and methodology •6+ years of experience with ASIC design and verification tools, techniques, and methodology •6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL. •6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills. •6+ years of experience with developing block-level testbench environment using SystemVerilog •6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification •6+ years of experience with scripting/automation skills using either Perl or python Qualifications: •Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. •Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience. •PhD in Science, Engineering, or related field. •Qualifications •Bachelor's degree in Engineering, Science, or a closely related field •2+ years of experience with ASIC design and verification tools, techniques, and methodology •Preferred Qualifications •Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field •6+ years of experience with ASIC design and verification tools, techniques, and methodology •6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL. •6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills. •6+ years of experience with developing block-level testbench environment using SystemVerilog •6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification •6+ years of experience with scripting/automation skills using either Perl or python •Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory) Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!