Hiring: ASIC Design Verification Engineer Company: Broadcom Location: Irvine, CA Job Posted Time: 2026-09-14 13:07:09 Target Skills & Keywords : Perl, Python, SystemVerilog, Verilog About the job Experience: •12+ years of related experience or Masters degree and 10+ years of related experience or PhD and 3+ years of related experience Required Skills: •Would you like to become part of a stable team developing silicon products for Ethernet systems in the Cloud •? Come join this team creating devices that accelerate AI/ML workflows •Develops high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency. •Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using •. You can become a member of an extremely skilled and efficient group of engineers. •. The candidate will work with our worldwide design and architecture teams to develop leading edge products. •All aspects of Design Verification will be involved, along with opportunities for technical leadership. •Constrained random verification methodologies with experience driving completion via coverage closure Compensation: •$129,400 - $207,000 / year •Competitive benefits and rewards package Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!