Analog IC Layout Engineer
Neuralink - South San Francisco, CA
Hiring: Analog IC Layout Engineer Company: Neuralink Location: South San Francisco, CA Job Posted Time: 2026-09-03 10:34:29 Employment Type: Full-time Target Skills & Keywords : Agile, C, C++, Capacitor, Python, SOC, Shell About the job Experience: •2+ years of experience in analog and mixed-signal IC layout design •1+ year experience with FinFET technologies Required Skills: •The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. •Crafting state-of-the-art layouts for mixed-signal and analog circuits •Power management circuits •Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers •Physical verification of custom IC mask layouts (LVS, DRC, ERC) Qualifications: •Bachelor of Science in Computer Engineering or related field •Demonstrated capacity to identify the best approach to solving problems •Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python •Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption •Understanding on failure-prone circuit and layout structures •Base Salary Range:: $83,000 USD - $139,000 USD Compensation: •Excellent medical, dental, and vision insurance through a PPO plan Interested candidates, please apply directly through the job posting on company's career page or try via AI auto apply on this platform. Don't miss this opportunity to join a forward-thinking team!